Generally, a phase locked loop (PLL) generates an output signal associated with a phase related to a phase of an input signal. Some PLLs use a counter to report an integer phase of a digitally controlled oscillator (DCO). Additionally, some PLLs use a time-to-digital converter (TDC) to report a fractional phase of the DCO. However, managing power consumption and area associated with a PLL or a TDC becomes challenging with more advanced technology.